1. Field of the Invention
The invention generally relates to computer systems and, in particular, to the handling of translation lookaside buffer (TLB) misses within a computer system capable of performing speculative memory access operations.
2. Description of Related Art
Current state of the art microprocessors typically include one or more components for facilitating the processing of memory access operations. One such component is a data cache unit ("DCU") which stores a portion of data within a high speed memory. Typically, data from the most recently accessed external memory locations are stored within the DCU such that, if access to the data is required again, the data need not necessarily be retrieved from external memory. Another component commonly employed is the TLB which caches linear addresses and corresponding physical addresses for use in microprocessors wherein data is internally processed using only linear addresses. The TLB is used in connection with a page miss handler ("PMH") which performs a translation of a linear address to a physical address for those addresses not cached within the TLB. In use, the TLB is initially accessed to determine whether the TLB contains the physical address corresponding to a linear address for a desired memory location. If the linear and physical address are not cached within the TLB, then the PMH performs a page table walk to determine the physical address corresponding to the desired linear address. Typically, once the TLB detects a first miss and the PMH is activated to perform the page table walk, the TLB does not process further address translations. Such a TLB is referred to as a blocking TLB because it blocks further address translations while a previous TLB miss is being processed.
DCU, TLB and PMH memory systems components may be provided within microprocessors capable of performing operations either out-of-order or speculatively. Out-of-order processing occurs when a microprocessor executes a micro-instruction, herein also referred to as an instruction, in advance of a later-generated instruction. In other words, actual execution of instructions need not be performed in the same order in which the instructions are generated or in which the instructions appear in a software program. Speculative processing occurs in a microprocessor capable of executing instructions which occur subsequent to a branch condition, such as an "If" statement, before the branch condition is actually resolved. In such systems, the microprocessor "guesses" as to which of two or more branches is likely to be taken. Such operations are termed "speculative" since it is not known whether the operations can actually be committed until the branch condition is resolved. If the branch prediction is found to be correct, then the speculatively executed instructions are merely committed to memory, i.e., the speculative instructions are "retired". If the branch prediction is found to be incorrect, then the speculatively executed instructions must be squashed or flushed from the system.
As can be appreciated, the capability of performing operations speculatively can result in a great windfall in processing speed. Since the microprocessor need not wait for a branch condition to be resolved prior to executing subsequent instructions. The advantages of performing operations out-of-order or speculatively are ideally exploited in microprocessors which are also capable of pipelined executions wherein two or more operations are performed simultaneously.
Microprocessors capable of out-of-order or speculative execution of instructions are described in "Superscalar Microprocessor Design" by Mike Johnson, Prentice-Hall, Inc. 1991.
Although speculative processing has considerable advantages over non-speculative processing, certain questions arise while implementing a TLB within microprocessors capable of speculative execution. For example, if a TLB miss is detected for a speculative memory instruction, a question arises as to whether the TLB should block further address translations pending completion of the page table walk triggered in response to the miss. If the miss triggering the initial page table walk is a speculative instruction resulting from a mis-predicted branch, it may be wasteful to block further address translations pending completion of the page table walk. As such, it would be desirable to implement a TLB which is non-blocking in response to a TLB miss especially within a microprocessor capable of speculative or out-of-order execution of memory instructions and it is to that end that certain aspects of the invention are drawn.